1. Technical Field
This invention relates to analog circuits for converting an input voltage into an output current, and more particularly to programmable analog circuits for converting an input voltage into an output current.
2. Description of the Related Art
A transconductor is a circuit which receives an input voltage and generates an output current. The magnitude of the output current is proportional to the input voltage received, and the ratio by which the output current changes. The ratio of output current change to input voltage change is known as the conversion gain, or transconductance (Gm=xcex94IOUT/xcex94VIN) of the transconductor. A differential transconductor receives a differential voltage impressed between two voltage input terminals, and generates a differential current between two current output terminals. The common-mode voltage of the two voltage input terminals is ignored.
A typical prior art differential transconductor art is shown in FIG. 1. A differential input voltage, VINNxe2x88x92VINP, is received between voltage input terminals 42 and 52, and a corresponding differential output current is generated between current output terminals 48 and 58. Current source circuit 30 includes current source 32 which delivers a current of magnitude I0 into summing node 36 and current source 34 which delivers a current of magnitude I0 into summing node 38. Input circuit 40, includes a gain block (e.g., operational amplifier (op-amp)44) having a non-inverting input coupled to the voltage input terminal 42 and an inverting input coupled to the summing node 36. The output of op-amp 44 drives the gate of transistor 46, which is a p-channel MOS transistor. Transistor 46 couples summing node 36 to current output terminal 48. Similarly, a second input circuit 50, includes an op-amp 54 having a non-inverting input coupled to voltage input terminal 52 and an inverting input coupled to summing node 38. The output of op-amp 54 drives the gate of transistor 56, which is also a p-channel MOS transistor. Transistor 56 couples summing node 38 to current output terminal 58. Resistor 35 (having the value R) couples summing node 36 to summing node 38. As is common with differential circuits, current source 32 and input circuit 40 are matched to current source 34 and input circuit 50, respectively, to provide balanced differential operation.
The operation of this circuit can best be understood by looking initially at the left-most portion. Input circuit 40 functions to force the voltage of summing node 36 to follow input voltage, VINN, received on voltage input terminal 42. This occurs because op-amp 44 drives the gate of transistor 46 to a suitable voltage such that the voltage of summing node 36, which is coupled to the inverting input of op-amp 44, follows the input voltage, VINN, coupled to the non-inverting input of op-amp 44. For example, if the voltage of summing node 36 is too high, the output of op-amp 44 is driven lower, thus providing corrective gate drive to p-channel MOS transistor 46. Consequently, a higher current flows through transistor 46 which lowers the voltage of summing node 36 until the voltage at summing node 36 is equal (or substantially equal) to the voltage at non-inverting input terminal of op-amp 44. The right-most portion of the transconductor of FIG. 1 operates in a similar fashion.
Thus, with the voltage of summing node 36 following input voltage VINN and the voltage of summing node 38 following input voltage VINP, the differential input voltage VINNxe2x88x92VINP is placed across resistor 35, and causes a current IS of magnitude (VINNxe2x88x92VINP)/R to flow from summing node 36 to summing node 38. If VINP is greater in magnitude than VINN then a negative current IS flows from summing node 36 to summing node 38 which is equivalent to a positive current flow from summing node 38 to summing node 36.
Summing node 36 receives a current lo from current source 32, and sources a current IS flowing into summing node 38. Thus, the net current which is provided to the source of transistor 46 is I0xe2x88x92IS. The current, IOUTN, coupled to current output terminal 48 must also be equal to I0xe2x88x92IS because the sum of currents received into any node must equal zero. Similarly, summing node 38 receives current 10 from current source 34, and receives a current IS flowing from summing node 36. The net current received into summing node 38 is I0+IS, which is coupled by transistor 56 to the current output terminal 58 as IOUTP=I0+IS.
The topology of the circuit in FIG. 1 is generally known as a degenerated pair linearized by servo-feedback, or a linearized resistor-based transconductor. The use of a resistor in setting the conversion gain of the transconductor generally results in high linearity, but also results in a conversion gain which is fixed by the choice of resistor value, and which varies with semiconductor process parameter variations. Consequently, programmable transconductors have been developed to allow selecting of the desired conversion gain after semiconductor manufacturing by, for example, a programmable resistor circuit.
An example of such a programmable transconductor can be found in U.S. Pat. No. 5,510,738, entitled xe2x80x9cCMOS Programmable Resistor-Based Transconductor,xe2x80x9d by James L. Gorecki and Yaohua Yang, (the xe2x80x9c""738 patentxe2x80x9d) which is incorporated herein by reference in its entirety.
FIG. 2 shows a programmable transconductor such as those disclosed in the ""738 patent. In many aspects, the programmable transconductor of FIG. 2 is similar to the transconductor of FIG. 1. Input circuit 40 includes an op-amp 44 (functioning as a gain block) having a non-inverting input coupled to voltage input terminal 42 and an inverting input coupled to first feedback node 60. The output of op-amp 44 drives the gate of transistor 46, which couples summing node 36 to current output terminal 48. Similarly, input circuit 50 includes op-amp 54 having a non-inverting input coupled to voltage input terminal 52 and an inverting input coupled to a feedback node 70. The output of op-amp 54 drives the gate of transistor 56, which couples summing node 38 to the current output terminal 58.
In further contrast to the transconductor of FIG. 1, the programmable transconductor of FIG. 2 includes circuit 37A having an array of switch circuits (62, 64, 66, 72, 74, and 76) and including a resistor circuit having a total resistance of R coupling summing node 36 to summing node 38. The resistor circuit includes resistors 63, 65, 69, 75, and 73 connected in series and defining a group of intermediate nodes 67, 68, 78, and 77 respectively therebetween. These intermediate nodes, together with summing nodes 36 and 38, form a group of tap nodes of the resistor circuit.
Switch circuits 62, 64, and 66 couple summing node 36 to feedback node 60 when enabled by logical signals S3, S2, and S1, respectively. Switch circuits 72, 74, and 76 couple summing node 38 to feedback node 70 when enabled by logical signals S3, S2, and S1, respectively. Logical signals S1, S2, and S3 are preferably digital control signals which select the desired transconductance of the circuit, but may also be a hardwired or some other fixed connection.
In operation, the programmable transconductor of FIG. 2 can be understood by assuming (for example) that logical signal S2 is active, and thus switch circuits 64 and 74 are enabled and remaining switch circuits 62, 66, 72, and 76 are disabled. Since intermediate node 67 is coupled to feedback node 60 which is coupled to the inverting input of op-amp 44, input circuit 40 functions to force the voltage of feedback node 60 and intermediate node 67 to follow the voltage VINN, received on voltage input terminal 42. If VINN is greater than VINP, and thus IS is positive, op-amp 44 drives the gate of transistor 46 to a suitable voltage such that the voltage of summing node 36 is driven to a voltage higher than VINN, so that the voltage of feedback node 60, which is coupled to the inverting input of op-amp 44, follows the input voltage VINN.
Input circuit 50 functions to force the voltage of intermediate node 77 to follow the voltage, VINP, received on voltage input terminal 52. Thus, with feedback node 60 following input voltage VINN and feedback node 70 following input voltage VINP, and since no DC current flows through switch circuits 64 and 74 (due to the high input impedance of op-amps 44 and 54), the differential input voltage VINNxe2x88x92VINP is placed directly across an effective resistance, Reff, consisting of resistors 65, 69, and 75 (since for this discussion logical signal S2 is active). This causes a current IS of magnitude (VINNxe2x88x92VINP)/Reff to flow from summing node 36 to summing node 38. If VINP is greater in magnitude than VINN then a negative current IS flows from summing node 36 to summing node 38 which is equivalent to a positive current flow from summing node 38 to summing node 36.
However, it can be seen from FIG. 2 that even though the magnitude of the current IS is set by the input differential voltage VINNxe2x88x92VINP across the effective resistor, Reff, formed by those resistors connected between the selected tap nodes, the current IS flows through all the series-connected resistors connected between summing nodes 36 and 38. Because IS (VINNxe2x88x92VINP)/Reff, higher conversion gain is accomplished by smaller values of effective resistance. By programming the switch circuits of circuit 37A, the conversion gain can be changed. Consequently, the voltage across the full resistor circuit increases as the gain increases. In other words, if tap points are selected that achieve a gain of 2, the total voltage drop across the entire resistor circuit also increases by a factor of 2. Because the total available voltage swing across the resistor circuit is limited by various operating conditions (e.g., supply voltage, input common-mode voltage, the threshold voltage of PMOS and other devices, etc) it is desirable to avoid large voltage swings across the resistor circuit. On the other hand, it is also desirable to achieve large gain. Thus, as gain increases, it becomes increasingly difficult to establish a large voltage across the resistor circuit for the practical limitations previously stated.
Accordingly, it is desirable to have a programmable transconductor that maintains a variety of programmable gain levels and high gain accuracy while still allowing large input signal and common-mode ranges.
It has been discovered that an improved programmable transconductor can be efficiently implemented utilizing a programmable resistor circuit that allows for only a selected portion of the resistor circuit (associated with a desired transconductor gain) to be coupled between summing nodes of the transconductor. Additional switching circuits can be used to reduce gain errors associated with the switches used to implement the aforementioned solution. Additionally, the improved programmable transconductor can be integrated into fully differential programmable analog integrated circuits, thereby enhancing the performance of such integrated circuits.
Accordingly, one aspect of the present invention provides a programmable transconductor for generating a differential current between first and second current output terminals responsive to a differential voltage applied between first and second voltage input terminals. The programmable transconductor includes first and second summing nodes, and first and second feedback nodes. The programmable transconductor also includes a resistor circuit including a plurality of resistors connected in series and defining a plurality of intermediate nodes, respective ones of the plurality of intermediate nodes being located between adjacent resistors of the plurality of resistors. The programmable transconductor is configured to selectively couple at least one of the plurality of resistors between the first summing node and the second summing node and to leave remaining ones of the plurality of resistors uncoupled from the first summing node and the second summing node. A switch circuit is coupled between a first one of the plurality of intermediate nodes and one of: the first summing node and the second summing node. A first input circuit is coupled to the first summing node and the first voltage input terminal. The first input circuit biases the first summing node to a suitable voltage so as to bias the first feedback node to a voltage substantially equal to a voltage applied to the first voltage input terminal. A second input circuit is coupled to the second summing node and the second voltage input terminal. The second input circuit biases the second summing node to a suitable voltage so as to bias the second feedback node to a voltage substantially equal to a voltage applied to the second voltage input terminal.
Another aspect of the present invention provides a programmable analog integrated circuit for receiving a differential analog input signal and providing a processed differential analog output signal, the programmable analog circuit. The programmable analog integrated circuit includes a first programmable analog circuit block having first analog circuit block positive and negative input terminals, first analog circuit block positive and negative output terminals, and the programmable transconductor of the present invention. The programmable analog integrated circuit also includes an analog routing pool. The analog routing pool controls the routing of the differential analog input signal and signals provided by and to the first programmable analog circuit block. The analog routing pool is programmable.
Yet another aspect of the present invention provides a programmable transconductor for generating a differential current between first and second current output terminals responsive to a differential voltage applied between first and second voltage input terminals. The programmable transconductor includes first and second summing nodes, and first and second feedback nodes. A current source circuit is configured to deliver a current to each of the first summing node and the second summing node. The programmable transconductor also includes a resistor circuit including a plurality of resistors connected in series and defining a plurality of intermediate nodes, respective ones of the plurality of intermediate nodes being located between adjacent resistors of the plurality of resistors. The programmable transconductor is configured to selectively couple at least one of the plurality of resistors between the first summing node and the second summing node and to leave remaining ones of the plurality of resistors uncoupled from the first summing node and the second summing node. A first plurality of switch circuits is included, each having a first terminal coupled to a corresponding intermediate node of the resistor circuit, and each further having a second terminal coupled to the first summing node. A second plurality of switch circuits is included, each having a first terminal coupled to a corresponding intermediate node of the resistor circuit, and each further having a second terminal coupled to the second summing node. A third plurality of switch circuits is included, each having a first terminal coupled to a corresponding intermediate node of the resistor circuit, and each further having a second terminal coupled to the first feedback node. A fourth plurality of switch circuits is included, each having a first terminal coupled to a corresponding intermediate node of the resistor circuit, and each further having a second terminal coupled to the second feedback node. A first gain block includes a first input coupled to the first voltage input terminal, a second input coupled to the first feedback node, and an output. A first transistor includes a first current-handling terminal coupled to the first summing node, a second current-handling terminal coupled to the first current output terminal, and a control terminal coupled to the output of the first gain block. A second gain block includes a first input coupled to the second voltage input terminal, a second input coupled to the second feedback node, and an output. A second transistor includes a first current-handling terminal coupled to the second summing node, a second current-handling terminal coupled to the second current output terminal, and a control terminal coupled to the output of the second gain block.
The foregoing is a summary and this contains, by necessity, simplifications, generalizations and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting. As will also be apparent to one of skill in the art, the operations disclosed herein can be implemented in a number of ways, and such changes and modifications can be made without departing from this invention and its broader aspects. Other aspects, inventive features, and advantages of the present invention, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth below.